Analog to digital converter



y 1957 H. J. GRAY, JR.. ET AL 2,791,764

ANALOG TO DIGITAL CONVERTER Filed Dec. 5, 1955 5 Sheets-Sheet 1 TO VERTICAL DEFLECTION PLATES /l3 I9 23 CATHODE ANALOG INPUT RAY CYCL'O PHOTO TUBE MASK TUBE TO 25 HORIZONTAL I DEFLECTION PULSE FORMING I PLATES CIRCUITS l 27 SWEEP /l7 oIRcuIT CYCLIC To FIG. I BINARY CONVERTER COMMAND TRIGGER SOURCE BINARY OUTPUT LEAST SIGNIFICANT MOST SIGNIFICANT CYCLIG DECIMAL DIGIT DIGIT OUTPUT EQUIVALENT saia- O-NOl-AOIONIQQE,

. INVENTORS F I G 2 HARRY J. GRAY. JR. PUZANT v, LEVONIAN y MORRIS RUBINOFF gfiozmiys May 7, 1957 H. J. GRAY, JR., ET AL 2,791,764

ANALOG TO DIGITAL CONVERTER Filed Dec. 5, 1955 s Shee'ts-Sheet 2 BINARY COUNTER CYCLIC "0R" GATE CLEAR 29 INPUT "AND" GATE GATE DELAY LINE CLOCK LENGTH NUMBER LENGTH PULSES BINARY COUNTER "OR" FIG 4 \GTE "AND" BINARY CLOCK GATES OUTPUT PULSES DELAY LINES "AND" GATES FENGTH CLOCK A PULSES INVENTORS HARRY J. GRAY, JR. PUZANT v. LEVONIAN BY MORRIS RUBINOFF May 7, 1957 Filed Dec. 5, 1G55 ANALOG ET AL TO DIGITAL CONVERTER 3 Sheets-Sheet 5 BINARY COUNTER CYCLIC INPUT BINARY COUNTER CYOLIC INPUT FLIP-FLOP "AND" GATE CLOCK PULSES DELAY LINES "AND" B|NARY LENGTH=NUMBER ATE LENGTH G OUTPUT "0R" GATE CLOCK FE PULSES "AND" GATE F I G 5 CLOCK PULSES o I INHIBITED "AND" GATE AND GATE INHIBITOR 'NPUT BINARY CLOCK DELAY LINE OUTPUT LENGTH=NUMBER GATE LENGTH F I G 6 "AND" GATE United States Patent ANALOG TO DIGITAL CONVERTER Harry J. Gray, Jr., Puzant V. Levonian, and Morris Rubinoif, Philadelphia, Pa., assignors, by mesne assignments, to the United States of America as represented by the Secretary of the Navy Application December 5, 1955, Serial No. 551,185

2 Claims. (Cl. 340-347) This invention relates to improvements in analog to digital converters for serial computing machines, and more particularly pertains to analog to digital converters for converting a cyclic number into its binary form serially with least significant digit first.

Where the magnitude of an analog quantity is required in digital form in a serial computing machine, methods used to date worked only with the most significant digit first, so that a reversing process was necessary before the number could be read into the machine. This imposes severe limitations on the speed of conversion. To overcome this disadvantage, the subject invention accomplishes the conversion of the analog number from its voltage-analog representation as a time sequence with the least significant digit first. The conversion is sufficiently fast to allow N numbers to be converted in N-l-l number-times, even for the fastest existing serial computing machines.

The process of conversion employed in the subject invention occurs in two steps. First, the number is converted from its voltage representation to a reflected binary or cyclic code with the least significant digit first. Second, the resultant cyclic number is transformed to its binary representation, the transformation being carried out least significant digit first.

The primary object of this invention is to provide an improved analog to digital converter for serial computing machines.

Another object is to provide an analog to digital converter whose output can be read synchronously into a high-speed digital computer by using cyclic to binary translators capable of converting a cyclic number into its binary form serially with the least significant digit first.

Other objects and many of the attendant advantages of this invention will be readily appreciated as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings wherein;

Fig. 1 is a block diagram of an analog to digital converter, showing a preferred embodiment of the invention; Fig. 2 is a plan view of a cyclic mask element; and

Figs. 3, 4, 5 and 6 show alternative forms of cyclic to binary converters.

In the following discussion of theoretical considerations, for any number A, the binary representation is Written as A2 and the cyclic representation as Ac. The arabic letters aj and bi designate digits of the binary numbers, and the Greek letters Aj and Bi designate digits of the cyclic numbers.

The cyclic code is derived from the binary notation by a single column shift followed by a logical addition, or addition without carry. Thus the binary number ice becomes the cyclic number Ac=om-1 an-z a1 a0 where om-r=an-r and ajE(a1+(l7'+1) (mod 2), i=0, 1 n2 where mod 2 addition of two binary digits is addition without carry. Further, it is to be noted that a =0, 1 as tlj=llj+1 or 677 01-14 respectively.

Illustrating the process for the number thirteen": shifted A2= l 1 0 1 A2: 1 1 0 (l) This leads to consideration of the following three theorems:

Theorem I: The cyclic representations of any pair of successive numbers, A and A+1 (:B), differ in only one column.

Proof: Let A2=anlan2 arao,

( 1) Suppose ao=0. Then [10:1 and a=b for j O.

Hence BoEbo+b1El+ar; ocoztl0+11=l1 r i+ r+r= i+ r+rzan H In this case, Ac diifers from Be only in column i=0.

(2) Let ao=l, the only other possible case. Then,

Consider column i=0:

Hence 50:110.

Consider next column i=1. We note in this case that b1=1+a1. If ar=0 the argument of part (1) applies,

Br ocr, B7=cj for f l and the theorem holds; if 111:1, then IJE1+Z2, the argument of part (2) holds, Br=oc1, but column i=2 must be inspected.

The process may be continued until (a) it terminates at column k (nl) with fika oclc, Bj=0tj for j k in which case the theorem holds, or (b) fly-=0 for (nl) and bn-1Ean r+l. In the latter case, since there is no column n, Bn-r an-r whether (In-1:0 or 1. This completes the proof of the theorem.

Theorem II: The parity of Ac is even or odd accord ing as ao=0 or 1.

Proof: The parity of Ac is by definition the sum of the digits or; of Ac, to modulus 2. But from Equation 1 it is seen that .'.Pan'ty of Ac=ao Theorem III: if

In generating the cyclic representation from the voltage analog, the analog input 11 is placed on the vertical de flectionplates of a cathode ray tube 13. Through a command trigger pulse derived from a source 15 and fed through a sweep circuit 17, the electron beam sweeps horizontally across the face of the tube 13- with constant velocity. A cyclic mask 19, quantized into distinct vertical levels, is placed in front of the tube 13. In the mask, at't-he verticallevel corresponding to .the:number'A, holes are provided .to'represent AI in-cyclicnotation. The. mask for a four digit output is shown in'Fig. .2, the slotsZl thereof being so placed thatyatagivenlevel, the digits of the:number appearin increasing order of significance from left to right. This is the reverse of the orderin which the numbers are written normally. They are placed this way so as to obtain the least significant digit of the cyclic outpuLfirst, withmthe. election beam sweeping from left to right. The mask indicates the numbers corresponding to the sixteen vertical levels in both decimal and cyclic form.

As-the beam sweeps across the face of the tube'13 from left to right, the lightlthat passes through the holes'21 in the mask is picked up by the photo-tube 23 and converted by pulse-forming circuits 25 into serial voltage pulses'that represent, with the least significant digit first, the cyclic equivalent of the analog voltage input. The output of circuits 25 is fed to: a cyclic to 'binaryconverter 27, hereinafter described, to produce the binaryoutput.

The advantage. of using a cyclic mask stems from the proposition that thc cyclic representations of any pair of successive numbers, A and A+l(=B), difier in only one column. If the electron beam sweeps between the levels representing two successive numbers, there is an ambiguity in one column only, and either one of these two successive numbers will be the resultant output Using a' binary mask, however, it is-possible fori'anambiguity to occur in several or all columns; a beam lying between the levels. representing binary seven (0111) and binary eight ('lQOQ) for example, might result in any number between zero and fifteen, inclusive. 7

Since it was proved,-above, that the parity of Ac is even or odd according as ao= or 1, it follows that, in converting from cyclic code back to binary notation'with least significant digit first, the first digit as can be obtained by counting the number of ls mod (2) in Ac, using a binary counter initially reset to zero. .The final stated the counter determines. a0. Moreover, since rio+a, Ed (mod 2), and since, if x+y z (mod 2), then x-l-yzy (mod 2), then a +op Eot (mod 2), and a, can be obtained by adding 05 to a, in the binary counter. Similarly, a +l fonall j can be found-by addition in the counter, since aj+l=aj+otj (mod 2). Hence, the entire binary representation Az can be obtained by reading the cyclic number into the binary counter twice.

In the cyclic to binary converter shown in Fig. 3, the binary counter'29 is cleared initially to the 0 stage. The output is obtained by gating clockpulses with the 1 stage of the counter. The cyclic input is read to the counter twice, once to determine the least significant-digit of the binary output and a second time to produce the entire output. The second reading is iobtained by circulating the cyclic number through a delay line 31 back to the input of the counter.

The control .unitsof .a digital computer. generates the A and B input pulses. Since the duration of these pulses is approximately a complete number length, suitable means such as a flip fiop can beused to generate A and B. The B input prevents the cyclic number from circulating more than once, and the A input gates 'the correct portion of the output.

The operation of the converter of Fig. 3 is based upon the premise that an is Zero .or one. Since it has been proved above that, if x-l-yzz (mod 2), then x+yzy (mod 2), it follows that .the. two resulting binary representations are ls complements of each other. For example; for-Ac=ll, 'if'it is correctly assumed that ao=l, then the correct-binary counterpart 1101 is obtained.

[i However, if it is assumed incorrectly that [1 :0, then the incorrect binary number 0010 is obtained.

In the cyclic to binary converter shown in Fig. 4, when the cyclic number is read to the counter, both of these possibilities are generated by gating clock pulses with the opposing stages of the counter. These two binary outputs are delayed one number length until the cyclic input has been read completely to the counter. The correct output is then selected by the stage of the counter that is positiveby-the parity of the cyclic input. In this converter, it is to be noted that the initial setting of the counter is immaterial, asthe correct output is obtained in both cases. The A input is added to gate the correct portion of the output.

In the converter shownlin Fig. 5, several cyclic numbers can be converted in sequence. The cyclic number serves as an upset input of the binary counter, which in turn keeps track of Whether an even or odd number of ls has already appeared in the cyclic input. The outputs ot the binary counter are of opposite polarity and control separate AND gates, which in turn'feed delay lines capable of storing one number each. The clock pulses servingas input to the gates appear at the basic repetition rate, which is the same rate as the serial cyclic input of binary digits. Consequently, the two delay lines contain binary representations of the input just after the lastdigit of the cyclic input has been registered in the binary counter. Onedelayline contains the true binary, whilethe other contains a false binary representation: The state of. the counter, after the first cyclic number isreadin, is remembered by the flip-flop circuit. This releases.the counter from-the duty of selecting one of the two possible outputs, and it can thus be used immediately bythe second cyclionumber to be converted. .The trigger input to the flip-flop, C, occurs immediately after each cyclicnumber is read completely tothe counter.

Aserialdigital computer (not shown) contains-in its control unit the circuits necessary to provide pulse C at justthe right time after the cyclic input was first directed to the binary counter. This time is just after the last cylic input bitis registered inthe binary counter. As a result, the binary-counter controls whether the flipilop is set or reset by pulse C. The flip-flop remembers the state of the binary counter at C pulse time, and permits the latter to be used in converting-the next cyclic input number. At the same time, the flip-flop is connected to control two AND gates so that only the correct binary representation in the corresponding delay line is permitted to be emitted from-the OR gate. The binary output is directed into the computer through this latter point.

In the converter shown in Fig. 6, only one input is used, its complement being formed by an inhibitor circuit. While initial clearing of the counter is unnecessary, an A input is needed at the inhibitorgate to select the correctportion of the output.

The analog to digital converter here described isa system wherein 'N cyclic numbers can be converted in N+1' numbertimes. For example, using a four-digit cyclic mask with a 5 inch cathode ray tube that could accomn1odate'256 lines (an 8 digit mask). With the line separation 0.5 mm. and thehorizontal separation approximately one-half inch overall, resolution of vertical lines and correct operation at a one megacycle pulse rate obtains, with pulse resolution remaining adequate up to at least four megacycles.

Obviously many modifications and variations of the present invention are possible in the lightof the aboveteachings. It is therefore to be understood that within the scope of the appended claims the invention rnaybe practiced otherwise than as specifically described.

We claim:

1. In an analog to digital converter, a cyclic to binary converter comprising a binary counter adapted to receive a cyclic input, first and second AND gates fed by opposing stages of said counter respectively, clock pulses gated with said stages, first and second delay line circuits each having a length equal to Word length coupled to said first and second gates respectively, third and fourth AND gates fed by said first and second circuits respectively, fifth and sixth AND gates fed by opposing stages of said counter respectively and by pulsing means synchronized with the delivery of such cyclic input, a flip-flop circuit receiving the output of said fifth and sixth gates and feeding said third and fourth gates, and an 10 6 OR gate receiving the output of said third and fourth gates whereby a binary output is presented.

2. The combination of claim 1 wherein said flip-flop circuit comprises setting means delivering negative output polarity to said fourth gate and positive output polarity to said third gate, and resetting means delivering positive output polarity to said fourth gate and negative output polarity to said third gate.

No references cited. 

